High-Accuracy Computing on Low-Precision Hardware (HCLH)

To be held in conjunction with SC ‘26: The International Conference for High Performance Computing, Networking, Storage and Analysis located in Chicago, IL on November 15 - 20.

Workshop Overview

This workshop aims to bring together researchers, application scientists, system developers, and industry partners to explore algorithmic and implementation approaches enabling accurate scientific computing on low-precision hardware. As accelerators increasingly favor reduced-precision arithmetic for performance and energy efficiency, many scientific applications continue to require accuracy, stability, and reproducibility. Addressing this widening gap demands community-driven advances across algorithms and scientific software, spanning domain-informed and cross-cutting approaches while building toward reusable, precision-aware libraries and tooling infrastructure.

The workshop will feature invited talks and solicited works highlighting mixed-precision methods, error-aware and adaptive numerical algorithms, floating-point emulation libraries, and practical deployment on large-scale systems. The workshop emphasizes building community-driven software ecosystems for broad adoption across domains, reducing duplication, and accelerating impact. By fostering discussion among application developers, numerical experts, and hardware vendors, the workshop will establish best practices, share lessons, and strengthen academia–industry collaboration to make low-precision hardware a reliable component of scientific workflows.

Workshop Schedule

The workshop will feature invited talks, peer-reviewed paper presentations, and a panel discussion. The finalized schedule can be found below.

  • Time: Monday, 16 November 2026, 2:00pm – 5:30pm CST
  • Location: W181b
Time Session
2:00pm – 2:05pm High-Accuracy Computing on Low-Precision Hardware
Organizers: Reet Barik, Aditya Kashi, Piotr Luszczek, Paul Lin, Hao Lu, Balavignesh Vemparala Narayana Murthy
2:05pm – 2:30pm Invited Talk with Eric Nielsen, Senior Research Scientist with the Computational AeroSciences Branch at NASA Langley Research Center
Presenter: Eric Nielsen
2:30pm – 2:45pm Accepted Paper 1: Mixed-Precision Cholesky Factorization for Semidefinite Programming Using Ozaki Scheme II
Haruki Nakamae, Toshio Endo, Katsuki Fujisawa
2:45pm – 3:00pm Accepted Paper 2: No Bits Left Behind: A Precision-Preserving On-Wafer Reduction for FP64 GEMM
Varuni Katti Sastry, Venkat Vishwanath
3:00pm – 3:30pm Afternoon Break
3:30pm – 3:55pm Invited Talk with Rob Schreiber, Distinguished Engineer at Cerebras Systems
Presenter: Rob Schreiber
3:55pm – 4:10pm Accepted Paper 3: Error-Explicit Low-Precision Factorizations for Iterative Refinement
Joseph McLaughlin, Jee Choi
4:10pm – 4:25pm Accepted Paper 4: Optimizing Semiconductor Device Simulations through Low-Precision Arithmetic
Alexander Maeder, Denghui Lu, Nicolas Vetsch, Vincent Maillou, Anders Winka, Jiang Cao, Mauro Dossena, Alexandros Nikolaos Ziogas, Mathieu Luisier
4:25pm – 4:40pm Accepted Paper 5: DGEMM with Ozaki Scheme I/II on FP4 Tensor Cores: A Base-13 E2M1 Limb Representation
Shun-ichiro Hayashi, Daichi Mukunoki, Tetsuya Hoshino, Takahiro Katagiri
4:40pm – 5:25pm Mixed Precision at Scale: From Peak FLOPs to Trusted Science
Moderator: Piotr Luszczek
Panelists: Satoshi Matsuoka, Scott Atchley, Harun Bayraktar, Kasia Swirydowicz
5:25pm – 5:30pm Concluding Remarks

Invited speakers

Photo of Eric Nielsen

Eric Nielsen

NASA Langley Research Center

Eric Nielsen is a Senior Research Scientist with the Computational AeroSciences Branch at NASA Langley Research Center in Hampton, Virginia.

He received his PhD in Aerospace Engineering from Virginia Tech. Dr. Nielsen specializes in the development of computational aerodynamics software for the world’s most powerful computer systems. The software has been distributed to thousands of organizations around the country and supports major national research and engineering efforts at NASA, in industry, academia, the Department of Defense, and other government agencies. He has published extensively on the subject and has given presentations around the world on his work. Dr. Nielsen is a recipient of NASA’s Exceptional Achievement and Exceptional Engineering Achievement Medals as well as NASA Langley’s HJE Reid Award for best research publication.

Photo of Rob Schreiber

Rob Schreiber

Cerebras Systems

Rob Schreiber is a distinguished American computer scientist renowned for his foundational research in parallel computing, sequential and parallel algorithms for matrix computation, and compiler optimization.

Schreiber earned his Ph.D. from Yale University in 1977 and later held faculty positions at Stanford University and Rensselaer Polytechnic Institute. Transitioning to industry, he served as Chief Scientist at Saxpy Computer, Assistant Director of the Exascale Computing Lab at Hewlett Packard Labs, and currently operates as a Software Architect at Cerebras Systems.

A pioneer in parallel environments, Schreiber co-developed High Performance Fortran, co-authored the NAS Parallel Benchmarks, and was a key contributor to the sparse-matrix extension of MATLAB. His extensive honors include being named a SIAM Fellow in 2010 and an ACM Fellow in 2012 for his exceptional contributions to languages, compilers, and architectures for parallel scientific computing.

Panelists

Photo of Satoshi Matsuoka

Satoshi Matsuoka

RIKEN and Tokyo Institute of Technology

Satoshi Matsuoka has been the director of RIKEN Center for Computational Science (R-CCS) since 2018. He is responsible for developing the supercomputer Fugaku which has become the fastest supercomputer in the world in all four major supercomputer rankings in 2020 and 2021 (Top500, HPCG, HPL-AI, Graph500), along with multitudes of ongoing cutting edge HPC research being conducted, including investigating post-Moore era computing, especially the future Fugaku NEXT supercomputer.

He received many international acclaims, at the Tokyo Institute of Technology, where he still holds a professor position, to continue his research activities in HPC as well as scalable Big Data and AI. His longtime contribution for the computer science research was commended with the Medal of Honor with Purple ribbon by his Majesty Emperor of Japan in 2022.

Photo of Scott Atchley

Scott Atchley

Oak Ridge National Laboratory (ORNL)

Scott Atchley is a Distinguished R&D Staff Member and Chief Technology Officer with the Oak Ridge National Laboratory’s National Center for Computational Science. Scott focuses on understanding technology trends and application needs to guide future system procurements. Within the Oak Ridge Leadership Computing Facility (OLCF), Scott has contributed to the Titan, Summit, and Frontier projects. For Frontier, Scott served as the system architect. He reprises that role for OLCF’s upcoming sixth leadership system, Discovery. Scott also serves as the lead for the Quantum HPC Systems effort within DOE's Quantum Science Center.

Photo of Harun Bayraktar

Harun Bayraktar

NVIDIA Corporation (NVIDIA)

Since joining NVIDIA in 2017, Harun Bayraktar has been leading the Math Libraries organization which builds software to help accelerate applications in science, engineering, Quantum Computing, and artificial intelligence (AI). Prior to joining NVIDIA, Harun’s career path includes development of commercial HPC computational mechanics software and physics-based simulation research and technology development for advanced composites materials in aerospace. Harun holds a PhD in mechanical engineering from UC Berkeley.

Photo of Kasia Swirydowicz

Kasia Swirydowicz

Advanced Micro Devices, Inc. (AMD)

Kasia Swirydowicz is a Senior Member of Technical Staff (SMTS), Software Development Engineer, at Advanced Micro Devices (AMD).

Call for papers

Modern high-performance computing systems increasingly prioritize reduced-precision arithmetic such as FP16, BF16, TF32, FP8, and integer formats to improve performance and energy efficiency. At the same time, many scientific applications continue to require high accuracy, numerical stability, and reproducibility. This growing mismatch between hardware trends and application requirements presents a fundamental challenge for the HPC community. Given this changing landscape, the SC26 Workshop on High Accuracy Computing on Low Precision Hardware aims to build a cross-disciplinary community around precision-aware scientific computing by bringing together expertise from HPC, numerical analysis, computer architecture, compilers, libraries, and scientific application domains. In doing so, the workshop will provide a forum for researchers and practitioners from academia, national laboratories, and industry to discuss emerging techniques, practical deployment experiences, and evaluation methodologies that jointly consider performance, energy efficiency, and numerical fidelity.

A central goal of the workshop will be to advance scientifically reliable computation on low-precision hardware. The workshop will therefore welcome contributions on mixed-precision and precision-adaptive algorithms, floating-point emulation techniques such as FP64 emulation and Ozaki-style schemes, and alternative number systems such as posits. It will also cover methods for understanding numerical sensitivity, instability, and error propagation in scientific workloads; formal and empirical techniques for analyzing conditioning and robustness; algorithms, software, and runtime systems that adapt precision dynamically; and compiler and library support for precision-aware execution. Application case studies will also be in scope, including work in finite element methods, CFD, multiphysics, linear algebra, and AI-for-science workflows.

Topics will include but will not be limited to

  • Mixed-precision and precision-adaptive algorithms

  • Precision-aware iterative methods, solvers, and preconditioners

  • Floating-point emulation techniques, including FP64 emulation and Ozaki-style schemes

  • Alternative number formats and numerical representations, including posits and custom formats

  • Numerical stability, conditioning, error propagation, and robustness analysis, including formal and empirical methods

  • Tools for numerical debugging, verification, sensitivity analysis, and robustness evaluation

  • Compiler, runtime, and library support for precision-aware execution

  • Hardware/software co-design and use of low-precision accelerators for accurate scientific computing

  • AI-driven or agentic methods for precision-aware analysis, tuning, and transformation of scientific software

  • Application studies in areas such as FEM, CFD, multiphysics, linear algebra, and AI-for-science workflows

  • Benchmarking and evaluation methodologies that jointly consider performance, energy efficiency, and numerical fidelity

Submission

Authors are invited to submit manuscripts in English as technical papers of 4 to 8 pages in 2-column format (U.S. letter, 8.5” × 11”), excluding references, using the IEEE proceedings template. Submissions are double-blind. Submissions received after the due date, exceeding the length limit, or not appropriately structured may not be considered.

All manuscripts will be peer-reviewed and judged on correctness, originality, technical strength and significance, quality of presentation, and interest and relevance to the workshop attendees. Each submission will receive at least 3 reviews. The review period runs from the submission deadline to the notification date. Revisions are not accepted; decisions are final. Submitted papers must represent original unpublished research that is not currently under review for any other conference or journal. Submissions not following these guidelines will be rejected without review, and further action may include reporting the authors to the sponsors of the conference and appropriate bodies governing ethics in scientific research. At least one author of an accepted paper must register for and attend the workshop. Authors may contact the workshop organizers for more information.

Papers must be submitted electronically via SC’26 Submissions Portal under SC26 Workshop: HCLH’26: High-Accuracy Computing on Low-Precision Hardware.

The final papers will be published in the SC Workshops Proceedings.

For questions, contact:

Important dates

  • Submission deadline: 10 August 2026 14 August 2026

  • Notification of acceptance: 31 August 2026 4 September 2026

  • Camera-ready deadline: 21 September 2026 25 September 2026

Committees

Organizing committee

  • Reet Barik, Argonne National Laboratory (ANL)

  • Aditya Kashi, Oak Ridge National Laboratory (ORNL)

  • Hao Lu, Oak Ridge National Laboratory (ORNL)

  • Piotr Luszczek, MIT Lincoln Laboratory and University of Tennessee, Knoxville (UTK)

  • Paul Lin, NVIDIA Corporation (NVIDIA)

  • Balavignesh Vemparala Narayana Murthy, Synopsys, Inc.

Program committee

  • Markus Eisenbach, Oak Ridge National Laboratory (ORNL)

  • Taylor Childers, Argonne National Laboratory (ANL)

  • Hartwig Anzt, Technical University of Munich, Germany (TUM)

  • Sherry Li, Lawrence Berkeley National Laboratory (LBNL)

  • Rui Peng Li, Lawrence Livermore National Laboratory (LLNL)

  • Dilip Asthagiri, Oak Ridge National Laboratory (ORNL)

  • Thomas Gruetzmacher, NVIDIA Corporation (NVIDIA)

  • Esteban Rangel, Argonne National Laboratory (ANL)

  • Oscar Hernandez Mendoza, Oak Ridge National Laboratory (ORNL)

  • Pratik Nayak, Technical University of Munich, Germany (TUM)

  • Longfei Gao, Argonne National Laboratory (ANL)

  • Nicholson Koukpaizan, Oak Ridge National Laboratory (ORNL)

  • Kasia Swirydowicz, Advanced Micro Devices, Inc. (AMD)

  • Vitali Morozov, Argonne National Laboratory (ANL)

  • Natalie Beams, University of Tennessee, Knoxville (UTK)

  • Roman Iakymchuk, Uppsala University, Sweden

  • Sajal Dash, Oak Ridge National Laboratory (ORNL)